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Preliminary W45B512 512K x 1 SERIAL FLASH
GENERAL DESCRIPTION
The W45B512 is manufactured with Winbond' high performance CMOS WinFlash technology. The s Serial Flash is organized as 16 sectors of 4096 Bytes for the W45B512. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (#WP), chip enable (#CE), and hardware reset (#RESET). This device is offered in 8L SON and 32L PLCC package.
FEATURES
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Single 2.7 - 3.6V Read and Write Operations Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 Byte Serial Read with Single Command Superior Reliability - Endurance: 10,000 Cycles (Typ.) - 20 years Data Retention
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Automatic Write Timing - Internal VPP Generation End-of-Write Detection - Software Status 20 MHz Max Clock Frequency Hardware Reset Pin (#RESET) - Resets the device to Standby Mode TTL Compatibility Hardware Data Protection - Protects/Unprotects the device from Write operation
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* *
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Low Power Consumption - Active Current: 30 mA (Max.) - Standby Current: 15 A (Max.)
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Sector or Chip-erase Capability - Uniform 4 KByte sectors
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Packages Available 8L SON (5 x 6 mm), 32L PLCC
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Fast Erase and Byte-program - Chip-erase Time: 100 mS (Max.) - Sector-erase Time: 25 mS (Max.) - Byte-program Time: 50 S (Max.)
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
PIN CONFIGURATIONS BLOCK DIAGRAM
Address Buffers and Latches
X-Decoder
SuperFlash Cell Array
1 2 3 4
#CE SO #WP Vss 8L SON Top View
VDD #RESE T SCK SI
8 7 6 5
Control Logic I/O Buffers and Data Latches Y-Decoder
Serial Interface
#CE
# R E S E T
SCK SI
SO #WP #RESET
N C 4 NC NC NC NC NC NC NC #CE NC 5 6 7 8 9 10 11 12 13
N C 3
NN CC 2 1
V D D
S C K
PIN DESCRIPTION
SYMBOL
29 28 27 SI NC NC NC NC #WP NC NC NC
32 31 30
PIN NAME Chip Enable Serial Data Input Serial Data Output Serial Clock Write Protect Reset Power Supply Ground
#CE SI SO SCK #WP #RESET VDD VSS
32L PLCC
26 25 24 23 22 21
14 15 16 17 18 19 20 SN OC V S S N C N C N C N C
PRODUCT IDENTIFICATION
BYTE Manufacturer' ID s Device ID: W45B512 0000 h 0001 h DATA DA h 98 h
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Preliminary W45B512
FUNCTIONAL DESCRIPTION
Device Operation
The W45B512 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in the table below. All instructions are synchronized off a high to low transition of #CE. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on #CE before the input instruction completes will terminate any instruction in progress and return the device to the standby mode.
Read
The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000h), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on #CE.
Sector/Chip-erase Operation
The Sector-Erase operation clears all bits in the selected sector to "FF". The Chip -Erase instruction clears all bits in the device to "FF".
Byte-program Operation
The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state ("FF") when initiating a Program operation. The data is input from bit 7 to bit 0 in order.
Software Status Operation
The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on #CE.
Reset
Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the #RESET pin. The device will remain in reset condition as long as #RESET is low. Minimum reset time is 10 S. See Figure 14 for reset timing diagram. #RESET is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on #CE is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to #RESET during the poweron process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on.
Read WINBOND ID/Read Device ID
The Read Manufacturer ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification codes. These codes may be used to determine the actual device resident in the system. Publication Release Date: February 21, 2002 Revision A1
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Preliminary W45B512
Write Protect
The #WP pin provides inadvertent write protection. The #WP pin must be held high for any Erase or Program operation. The #WP pin is "don' care" for all other operations. In typical use, the #WP pin is t connected to VSS with a standard pull-down resistor. #WP is then driven high whenever an Erase or Program operation is required. If the #WP pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The #WP pin has an internal pull-up and could remain unconnected when not used.
DEVICE OPERATION INSTRUCTION
BUS CYCLE Operation/Type Read Sector-erase 2 Chip-erase Byte-program Software-status Read Manufacture ID Read Device ID
Notes: 1. A23 - A16 are "Don't Care" for device. 2. A15 - A12 are used to determine sector address, A11 - A8 are don't care. 3. With A15 - A1 = 0, W45B512 Device ID = 98h, is read with A0 = 1.
3
1
2
1
3 Address
4 Address A7 - A0 X X A7 - A0 A0 = 0 A0 = 1
5 Data X Dout Dout Din
6 Dummy X X X X
7 Data Dout
Command Address FFh 20h 60h 10h 9Fh 90h 90h
A23 - A16 A15 - A8 A23 - A16 A15 - A8 X X A23 - A16 A15 - A8 Dout X X X X
DAh 98h
DEVICE OPERATION TABLE
OPERATION Read Sector-erase Chip-erase Byte-program Software-status Reset2 Read Manufacture ID Read Device ID SI X X X Din X X X X SO Dout X X X Dout X Dout Dout #CE1 Low Low Low Low Low X Low Low #WP X High High High X X X X #RESET High High High High High Low High High
Notes: 1. A high to low transition on #CE will be required to start any device operation except for Reset. 2. The #RESET low will return the device to standby and terminate any Erase or Program operation in progress.
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Preliminary W45B512
DC CHARACTERISTICS
Absolute Maximum Stress Ratings
(Applied conditions greater than those listed under "Absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) PARAMETER Temperature Under Bias Storage Temperature D. C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS) on Any Pin to Ground Potential Package Power Dissipation Capability (TA = 25 C) Surface Mount Lead Soldering Temperature (3 Seconds) Output Short Circuit Current 1 RATING -55 to +125 -65 to +150 -0.5 to VDD +0.5 -1.0 to VDD +1.0 1.0 240 50 UNIT C C V V W C mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD =2.7V - 3.6V, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITION MIN.
LIMITS MAX. 30 20 15 2 2 -0.2 2.0 0.6 VDD +0.3 0.4 UNITS mA mA A A A V V V V
Power Supply Current
IDD
f = 20 MHz #CE = VIL, VDD = VDD Max.
Program/Erase Read
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Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
ISB ILI ILO VIL VIH VOL
#CE = VIHC, VDD = VDD Max. VIN = GND to VDD, VDD = VDD Max. VOUT = GND to VDD, VDD = VDD Max.
IOL = 1.6 mA
2.4
VOH IOH = -0.4 mA
Note: Outputs shorted for no more than one second. No more than one output shorted at a time.
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
CAPACITANCE
(VDD = 2.7V ~ 3.6V, TA = 25 C, f = 1 MHz)
PARAMETER Output Pin Capacitance Input Pin Capacitance
SYMBOL COUT1 CIN1
CONDITIONS VDQ = 0V VIN = 0V
MAX. 12 6
UNIT pF pF
AC CHARACTERISTICS
AC Test Conditions
(VDD = 2.7V ~ 3.6V)
PARAMETER Input Rise/Fall Time Input/Output Timing Level Output Load <5 nS 0.5 VDD / 0.5 VDD CL = 30 pF
CONDITIONS
AC Test Load and Waveform
CL =30pF
V IHT INPUT V ILT VIT REFERENCE POINTS V OT OUTPUT
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0".Measurement reference points for inputs and outputs are at VIT (0.5 VDD) and VOT (0.5 VDD) Input rise and fall times (10% 90%) are <5 nS. Note: VIT: VINPUT Test; VOT: VOUTPUT Test; VIHT: VINPUT HIGH Test; VILT; VINPUT LOW Test
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Preliminary W45B512
AC Operating Characteristics
(VDD = 2.7V ~ 3.6V)
PARAMETER
SYMBOL MIN.
LIMITS MAX. 20 22 22 10 10 50 0 5 5 0 10 10 10 10 20 20 25 25 100 50 1 UNITS MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS mS mS S S S S
Serial Clock Frequency Serial Clock High Time Serial Clock Low Time #CE Setup Time #CE Hold Time #CE High Time #CE High to High-Z Output #CE Low to Low-Z Output #RESET Low to High-Z Output Data In Setup Time Data In Hold Time Output Hold from SCK Change Output Valid from SCK Write Protect Setup Time Write Protect Hold Time Sector-erase Chip-erase Byte-program Reset Pulse Width Reset Recovery Time Reset Time After Power-up
FCLK TSCKH TSCKL TCES TCEH TCPH TCHZ TCLZ TRLZ TDS TDH TOH TV TWPS TWPH TSE TSCE TBP TRST TREC TPURST
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
TIMING WAVEFORMS
Serial Input Timing Diagram (Inactive Serial Clock Low - Mode 0)
#WP
TCPH
#CE
TCES T SCKH T SCKL TCEH
SCK SI SO
TDS
T DH
DATA VALID
HIGH-Z
HIGH-Z
Serial Output Timing Diagram (Inactive Serial Clock Low - Mode 0)
#WP #CE SCK
TCLZ
TSCKH TSCKL
TCEH TCHZ
TOH
DATA VALID
SO
TV
SI
Serial Input Timing Diagram (Inactive Serial Clock High - Mode 3)
#WP
T CPH
#CE
T CES TSCKH TSCKL
SCK
TDS TDH
T CEH
SI SO
DATA VALID
HIGH-Z
HIGH-Z
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Preliminary W45B512
Timing Waveforms, continued
Serial Output Timing Diagram (Inactive Serial Clock High - Mode 3)
#WP #CE SCK
T CLZ TOH
DATA VALID
TSCKH TSCKL
T CEH
TCHZ
SO
TV
SI
Sector-erase Timing Diagram
TWPS #WP
TWPH
#CE 0 123456 78 SCK 15 16 23 24 31 32 39 40 47 TSE SELF-TIMED SECTORERASE CYCLE
SI SO
0 0 1 0 0 0 0 0 ADD.
ADD.
X
D0H
X
HIGH IMPEDANCE
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
Timing Waveforms, continued
Chip-erase Timing Diagram
TWPS #WP
TWPH
#CE TSCE 0 123456 78 SCK 15 16 23 24 31 32 39 40 47
SELF-TIMED CHIPERASE CYCLE
SI SO
01100000
X
X
X
D0H
X
HIGH IMPEDANCE
Byte-program Timing Diagram
TWPS #WP
TWPH
#CE TBP 47 SELF-TIMED BYTEPROGRAM CYCLE
SCK
0 123456 78
15 16
23 24
31 32
39 40
SI 0 0 0 1 0 0 0 0 ADD. SO ADD. ADD. Din X MSB LSB
HIGH IMPEDANCE
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Preliminary W45B512
Timing Waveforms, continued
Read Timing Diagram
#WP
#CE 0 123456 78 SCK SI SO 0 0 0 1 0 0 0 0 ADD. ADD. ADD. X X
N N+1 N+2
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71
HIGH IMPEDANCE
Dout
MSB
Dout
MSB
Dout
MSB
Read-Id Timing Diagram
#WP
#CE 0 123456 78 SCK SI SO 10010000 X X ADD Dout1
MSB LSB
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71
HIGH IMPEDANCE
Note: 1. Manufacturer's ID = DAh is read with A 0 = 0 Device ID = 98h is read with A 0 = 1
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
Timing Waveforms, continued
Software-Status Timing Diagram
#WP
#CE 0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 SCK SI SO 10011111
DATA MSB DATA MSB DATA MSB
23 24
31
HIGH IMPEDANCE
Reset Timing Diagram (Inactive Clock Polarity Low Shown)
#CE T REC SCK TRST #RESET SO SI HIGH IMPEDANCE T RLZ HIGH IMPEDANCE T CES
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Preliminary W45B512
Timing Waveforms, continued
Power-on Reset Timing Diagram
VDD
TPURST
#RESET #CE
TREC
Write Protect Timing Diagram
TWPS #WP
TWPH
TCPH #CE TCES SCK TCEH
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
ORDERING INFORMATION
PART NO. OPERATING VOLTAGE (V) W45B512Z W45B512P
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
POWER SUPPLY CURRENT MAX. (mA) 30 30
STANDBY VDD CURRENT MAX. (A) 15 15
PACKAGE
CYCLING OPERATING TEMP. (C)
2.7V - 3.6V 2.7V - 3.6V
8L SON (5 x 6 mm) 32L PLCC
10K 10K
0C - 70C 0C - 70C
HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W45B512
W45B512Z 2138977A-A12 149OBSA
1 line: winbond logo 2 line: the part number: W45B512Z 3 line: the lot number 4 line: the tracking code: 149 O B SA 149: Packages made in 01, week 49 ' O: Assembly house ID: A means ASE, O means OSE, ... etc. B: IC revision; A means version A, H means version H, ... etc. SA: Process code
th rd nd st
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Preliminary W45B512
PACKAGE DIMENSIONS
8L SON (5 x 6 mm)
32L PLCC
Symbol
HE E
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
4
1
32
30
5
29
GD D HD
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
13
21
14
20
c
L A2 A
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1 y
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Publication Release Date: February 21, 2002 Revision A1
Preliminary W45B512
VERSION HISTORY
VERSION A1 DATE Feb. 21, 2002 PAGE Initial Issued DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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